`timescale 1ns / 1ps

module IFID(
  input         clk,
  input         rst,
  input         stall,
  input         flush,
  input  [63:0] IF_pc,
  input  [31:0] IF_inst,
  input         IF_valid,
  input  [63:0] IF_pc_4,
  input         predict_jump_if,
  output reg [31:0] ID_inst,
  output reg [63:0] ID_pc,
  output reg [63:0] ID_pc_4,
  output reg        ID_valid,
  output reg        predict_jump_id
);

always @(posedge clk) begin
  if(rst|flush) begin
      ID_pc <= 0;
      ID_inst <= 0;
      ID_valid <= 0;
      ID_pc_4 <= 0;
      predict_jump_id <=0;
  end
  else if(~stall) begin
      ID_pc <= IF_pc;
      ID_inst <= IF_inst;
      ID_valid <= IF_valid;
      ID_pc_4 <= IF_pc_4;
      predict_jump_id <= predict_jump_if;
  end
end

endmodule